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Keith:
༼ຈل͜├┬┴┬┴ Psst, hey kid, wanna do some exploits?
Mojo:
http://i57.tinypic.com/1zw0x9s.gif
Chilli:
This circuit[23] consists of two stages implemented by SR NAND latches. The input stage (the two latches on the left) processes the clock and data signals to ensure correct input signals for the output stage (the single latch on the right). If the clock is low, both the output signals of the input stage are high regardless of the data input; the output latch is unaffected and it stores the previous state. When the clock signal changes from low to high, only one of the output voltages (depending on the data signal) goes low and sets/resets the output latch: if D = 0, the lower output becomes low; if D = 1, the upper output becomes low. If the clock signal continues staying high, the outputs keep their states regardless of the data input and force the output latch to stay in the corresponding state as the input logical zero (of the output stage) remains active while the clock is high. Hence the role of the output latch is to store the data only while the clock is low.
Keith:
!status call ins | Officially named my cat le toucan
Mojo:
During a manic phase of bipolar disorder, you may feel very happy and have lots of ambitious plans and ideas. You may spend large amounts of money on things you cannot afford and would not normally wan